A packaged semiconductor light emitting device (hereinafter, referred to as an “LED device” unless specified otherwise in particular) has been widely spread, in which a semiconductor light emitting element (hereinafter, referred to as an “LED die” unless specified otherwise in particular) cut out from a wafer is mounted on a lead frame or a circuit substrate and which is covered with a resin, glass, etc. There are a variety of aspects of the LED device in accordance with its use and there is a case where the planar size of the circuit substrate and that of the LED die are made substantially equal when the package is downsized. The package is one aspect of the chip size package (also referred to as CSP).
FIG. 10 is a section view illustrating a conventional light emitting diode.
FIG. 10 is a diagram illustrating FIG. 1 described in Patent Literature 1. The light emitting diode is connected onto a submount 118 (circuit substrate) by interconnection 117 in the state where a chip (LED die) is reversed (flip-chip). The chip is configured by stacking a substrate 110, an n-type semiconductor layer 112, an active region 114, a p-type region 115, and a contact 116 in the downward direction in FIG. 10. The top surface and the side surface of the chip are covered with phosphorescent layers 120 and 119 (phosphors).
The light emitting diode illustrated in FIG. 10 aims at improvement of light emission efficiency, and therefore, the sub mount 118 is drawn in a simplified manner, but the characteristic feature lies in that there is no underfill between the chip and the sub mount 118.
Patent Literature 1: Japanese Unexamined Patent Publication (Kokai) No. 2005-136420